USB 2.0 PHY IP Device/Host/OTG/Hub (Silicon proven in TSMC 40LP /LL)
Mixed-Signal Verification for USB 2.0 Physical Layer IP
TUSB1210 data sheet, product information and support | TI.com
The USB 2.0 Device IP core | Arasan Chip Systems
ASMedia Demos USB 3.2 Gen 2x2 PHY, USB 3.2 Controller Due in 2019
USB 3.0/2.0 Combo PHY IP for SoC Designs | Cadence IP
Having trouble getting USB PHY to work with STM32 : r/embedded
USB 2.0 Full High Speed Solution | NXP Semiconductors
USB 2.0 PHY for SoC Designs | Cadence IP
USB3300 USB HS Board USB high-speed PHY device for ULPI interface
Canovatech - CT25201_PHY
USB 2.0 Full High Speed Solution | NXP Semiconductors
The Next-Generation Interconnect | Mouser
USB 2.0 PHY IP core | Arasan Chip Systems
USB Device
Figure 2 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
USB 3.0 PHY IP Core
High Speed Inter-CHIP USB 2.0 PHY | Arasan Chip Systems
ULPI - Kcchao
USB PHY芯片 | 码农家园
Hi-Speed USB interfacing
TUSB1210-Q1 data sheet, product information and support | TI.com
PCIe/USB/SATA PHY Appilcation example | Renesas
